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Use n32:64 in RISC-V data layout #7175

Merged
merged 2 commits into from
Nov 28, 2022
Merged

Use n32:64 in RISC-V data layout #7175

merged 2 commits into from
Nov 28, 2022

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dkurt
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@dkurt dkurt commented Nov 22, 2022

related: llvm/llvm-project@974e2e6
resolves #7174

@steven-johnson
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LGTM, please push one more commit to trigger the buildbots

@zvookin
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zvookin commented Nov 28, 2022

Only question here is whether this should be conditional in the LLVM version. It looks like it was kind of always wrong. I guess the way to find out would be to make the change unconditional and see if if it still works with LLVM 15, but that may not be worth it. (The buildbots will not test that and I don't have an LLVM 15 tree handy.) Going to LGTM this.

@steven-johnson
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LGTM once buildbots are green.

@dkurt
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dkurt commented Nov 28, 2022

@zvookin, good point. Not sure if that will work but I can check with LLVM 15 as well. The less conditional compilation the better.

Actually, I used LLVM 15 when prepared #7166 so probably there was a different layout string.

@steven-johnson steven-johnson merged commit 3ff9e66 into halide:main Nov 28, 2022
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Thanks for the fix!

@dkurt dkurt deleted the patch-1 branch November 29, 2022 07:03
ardier pushed a commit to ardier/Halide-mutation that referenced this pull request Mar 3, 2024
* Use n32:64 in RISC-V data layout

* Remove unused LLVM header
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[RISC-V] Data layout mismatch between module
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